Design of a High Performance Vector Processor Based on RISIC-V Architecture

Abstract This paper proposes a high performance Vector processor based on the Embedded Core which is named TS800. The TS800 4-core RISC-V architecture, implements IMAFDV instruction set, supports L2 Cache, branch prediction, sequential pipeline, and dual-issue structure. traditional CPU mainly Scalar calculations, or only calculations. For applications such as image signal processing, there are large number of data parallel computing operations. To solve problem low calculations in industrial power applications, it proposed to add VPU hardware implementation can support FFT algorithm, adaptive controllers Reinforcement learning learning-based underlying algorithm requirements. In this paper, module flow between each processing unit control circuit, that is, realization proposed. Large-area units float arithmetic, multiplication division multiplexed with operator CPU, while circuit placed VPU-ALU, area small. Units arithmetic logic operation instructions, shift comparison permutation implemented through makes overall design smaller better. At same time, fir, fft, conv, matrix, Signal Converge variance test, proved executing program, running time cpu 1.44 9.55 times module, controller.